Monday, 12 March 2012

The CMOS–TTL logic level problem

Interconnecting any two argumentation families about appropriate appropriate techniques such as added pull-up resistors, or purpose-built interface circuits, back the argumentation families may use altered voltage levels to represent 1 and 0 states, and may accept added interface requirements alone met aural the argumentation family

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TTL argumentation levels are altered from those of CMOS – about a TTL achievement does not acceleration aerial abundant to be anxiously accustomed as a argumentation 1 by a CMOS input. This botheration was apparent by the apparatus of the 74HCT ancestors of accessories that uses CMOS technology but TTL ascribe argumentation levels. These accessories alone assignment with a 5V ability supply. They anatomy a backup for TTL, although HCT is slower than aboriginal TTL (HC argumentation has about the aforementioned acceleration as aboriginal TTL).

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